Tenders Are Invited For European Terabit Per Second Ethernet Packet Switch/Router Ip Core For Multi-Orbit Co ... in Netherlands The

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Tenders are invited for European Terabit Per Second Ethernet Packet Switch/Router IP Core for Multi-Orbit Constellations (Artes at 5c.540) Objective: The objective of the activity is to develop, manufacture and test an Ethernet switch/router Intellectual Property (IP)core and test chip supporting layers 1 to 3 packet processing for constellations. The IP core shall be developed, implemented on a test chip using the optimal UDSM ASIC technology node(s) selected as part of this activity to achieve the desired performance, and tested using a validation breadboard.Targeted Improvements: Enabling a European or Canadian source of terabit class ethernet switch/routers for multi-orbit constellation applications.Description: Cost sensitive, high volume multi-orbit constellation solutions require a tailored ethernet packet switch/router adapted to high data rates (at and above 100 Gbps), number of ports (16 and more) and supported protocols. An ethernet switch/router, scalable in data rate and number of ports and supporting layer 1 to 3 protocols, is not available from a European or Canadian supplier. Existing commercial solutions cannot be readily adapted to the needs of satcom applications in low earth orbit and multi-orbit constellations.This activity will be implemented in a phased approach. In Phase 1, an ethernet switch/router IP core shall be developed utilising ultra-deep sub-micron (UDSM) ASIC technology (targeting 7nm or below) to achieve 1 terabit per second data throughput for low earth orbit and multi-orbit constellation applications. The data rateper port and number of ports forming a channel shall be configurable to suit multiple applications (configurable number of ports from 4 to at least 16 ports, with configurable port data rate from 1Gbps to at least100Gbps per port). Multi-protocol label switchingand the internet protocol shall be supported. Phase 1 will conclude with the completed IP core design, verified and synthesised in the design environment, to generate the ASIC test chip tape-out files ready for fabrication. The budget for Phase 1 is up to 2,000 kEuro.In the second phase, the IP core will be implemented in the selected UDSM ASIC technology as an ASIC test-chip (via a Multi Project Wafer Run or shared Full Mask Run). A validation breadboard shall be designed and built to undertake performance testing of thetest chip. The test chip shall be representative of a scaled version of a final product and shall be tested in relevant environment.IP cores developed in this activity shall be available for further development by ESA Member State and Canadian industries at fair and reasonable market conditions Tender Link : https://esastar-publication-ext.sso.esa.int/ESATenderActions/filter/open

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