Contract Award Notice |
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TRR | 4509627 |
Organization | Government Engineering College |
Tender No | DOTE/GCE-SRI/420/ECE10/2020 |
Funded By | Self-Funded |
Country | India , Southern Asia |
Contract Value | 390,769 |
Work Detail |
Tender For Dsp Trainer Kits For Dsp Lab -1 Tms320c6748 Based Dsp Trainer Kit • Tms320c50 Operating At Around 40 Mhz. N• On-Chip Ram: 10K Word N• 32Kb Eprom With Communication Kernel. N• Analog Interface Chip With 14-Bit Analog To Digital Converter And 14-Bit Digital To Analog Converter With 16 Bit Dynamic Range. N• Programmable Sample Rate Up To 43 Khz. N• Programmable +3V / -3V Full Scale Input. N• Programmable +3V / -3V Full Scale Output Into 600 Ohms Load. It Can Drive An 8-Ohm Speaker Directly. N• Programmable Anti-Aliasing And Reconstruction Filters. N• Over Voltage Protection For Analog Inputs. N• Facility To Connect Mic And Speaker. N• Usb Port For Communicating With The Host Pc. N• With Assembler And The Dsp Debugging Software With Graphical User Interface. N• Power Supply And Function Generator Facility N• Rfi Filtered Linear Power Supply N• Output Frequency Up To 20 Khz. Over Voltage Protection For Analog Inputs. N 2 Tms320c5x Based Starter Kit Tms320c674x Fixed / Floating-Point Vliw Dsp Core N• 64 General-Purpose Registers ( 32 Bit ) N• Six Alu ( 32- / 40-Bit ) Functional Units N• Two Multiply Functional Units N• Instruction Packing Reduces Code Size N• All Instructions Conditional N• Hardware Support For Modulo Loop Operation N• Real Time Clock Non-Chip Memory: N?Two Level Cache Memory Architecture N? 32K-Byte L1p Program Ram / Cache N? 32K-Byte L1d Data Ram / Cache N? 256K-Byte L2 Unified Mapped Ram / Cache N? 128K-Byte Ram Shared Memory Nwith On-Board Features N• Jtag Emulator ( Xds100v1 ) N |
Key Dates |
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Contract Date | 26 Feb 2021 |
Contact Information |
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